An Efficient Fault Simulation Technique for Transition Faults in Non-Scan Sequential Circuits

Abstract : This paper proposes an efficient technique for transition delay fault coverage measurement in synchronous sequential circuits. The proposed strategy is based on a combination of multi-valued algebra simulation, critical path tracing and deductive fault simulation. The main advantages of the proposed approach are that it is highly computationally efficient with respect to state-of-the-art fault simulation techniques, and that it encompasses different delay sizes in one simulation pass without resorting to an improved transition fault model. Preliminary results on ITC'99 benchmarks show that the gain in terms of CPU time is up to one order of magnitude compared to previous existing techniques.
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Communication dans un congrès
DDECS'09: 12th IEEE Symposium on Design and Diagnostics of Electronic Systems, pp.50-55, 2009
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00371197
Contributeur : Alberto Bosio <>
Soumis le : jeudi 26 mars 2009 - 18:36:17
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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  • HAL Id : lirmm-00371197, version 1

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Alberto Bosio, Paolo Bernardi, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda. An Efficient Fault Simulation Technique for Transition Faults in Non-Scan Sequential Circuits. DDECS'09: 12th IEEE Symposium on Design and Diagnostics of Electronic Systems, pp.50-55, 2009. 〈lirmm-00371197〉

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