Evaluating the Robustness of Secure Triple Track Logic Through Prototyping

Rafael Soares 1 Ney Calazans 1 Victor Lomné 2 Philippe Maurine 3 Lionel Torres 3 Michel Robert 3
1 PUCRS - Pontifícia Universidade Católica do Rio Grande do Sul [Porto Alegre]
2 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
3 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Side channel attacks are known to be efficient techniques to retrieve secret data. Within this context, this paper proposes to prototype a logic called Secure Triple Track Logic (STTL) on FPGA and evaluate its robustness against power analyses. More precisely, the paper aims at demonstrating that the basic concepts on which this logic leans are valid and may provide interesting design guidelines to obtain secure circuits.
keyword : CPA DES DPA FPGA Logic Style Side-Channel Attacks
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CNRS | SYSMIC | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER

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Rafael Soares, Ney Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, et al.. Evaluating the Robustness of Secure Triple Track Logic Through Prototyping. SBCCI'08: Symposium on Integrated Circuits and Systems Design, Sep 2008, Gramado, Brazil, pp.193-198, ⟨10.1145/1404371.1404425⟩. ⟨lirmm-00373516⟩

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