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Evaluating the Robustness of Secure Triple Track Logic Through Prototyping

Abstract : Side channel attacks are known to be efficient techniques to retrieve secret data. Within this context, this paper proposes to prototype a logic called Secure Triple Track Logic (STTL) on FPGA and evaluate its robustness against power analyses. More precisely, the paper aims at demonstrating that the basic concepts on which this logic leans are valid and may provide interesting design guidelines to obtain secure circuits.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00373516
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Submitted on : Monday, April 6, 2009 - 11:47:02 AM
Last modification on : Thursday, March 31, 2022 - 11:10:08 AM
Long-term archiving on: : Thursday, June 10, 2010 - 6:04:53 PM

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Rafael Soares, Ney Calazans, Victor Lomné, Philippe Maurine, Lionel Torres, et al.. Evaluating the Robustness of Secure Triple Track Logic Through Prototyping. SBCCI'08: Symposium on Integrated Circuits and Systems Design, Sep 2008, Gramado, Brazil, France. pp.193-198, ⟨10.1145/1404371.1404425⟩. ⟨lirmm-00373516⟩

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