Prototyping Secure Triple Track Logic (STTL) Robustness Against DPA & DEMA on FPGA

Victor Lomné; Rafael Soares; Thomas Ordas; Philippe Maurine; Lionel Torres; Michel Robert

Conference papers

Prototyping Secure Triple Track Logic (STTL) Robustness Against DPA & DEMA on FPGA

Victor Lomné ¹ Rafael Soares ² Thomas Ordas ¹ Philippe Maurine ³ Lionel Torres ³ Michel Robert ³

1 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier

2 PUCRS - Pontifícia Universidade Católica do Rio Grande do Sul [Porto Alegre]

3 SysMIC - Conception et Test de Systèmes MICroélectroniques

LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier

Document type :

Conference papers

Domain :

Computer Science [cs] / Cryptography and Security [cs.CR]

Engineering Sciences [physics] / Micro and nanotechnologies/Microelectronics

Complete list of metadata

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00373539
Contributor : Victor Lomne Connect in order to contact the contributor
Submitted on : Monday, April 6, 2009 - 1:19:51 PM
Last modification on : Friday, October 22, 2021 - 3:07:38 PM

Prototyping Secure Triple Track Logic (STTL) Robustness Against DPA & DEMA on FPGA

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Prototyping Secure Triple Track Logic (STTL) Robustness Against DPA & DEMA on FPGA

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