Electrical Analysis of a Domino Logic Cell with GOS Faults - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2005

Electrical Analysis of a Domino Logic Cell with GOS Faults

Abstract

Gate-Oxide Shorts (GOS) have an increasing impact on the integrated circuit production yield due to the reduction of the related dimensions. The detection of GOS is a challenging issue in the field of testing. This paper presents a detailed study of the impact of a GOS fault affecting a Domino logic circuit. Indeed, Domino logic specific clocked operating principle induces a different behavior from standard full CMOS cells under the effect of a GOS, which can enable GOS detection. Finally, some clues to enhance GOS detection in Domino cells are proposed.
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Dates and versions

lirmm-00374937 , version 1 (10-04-2009)

Identifiers

  • HAL Id : lirmm-00374937 , version 1

Cite

Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell. Electrical Analysis of a Domino Logic Cell with GOS Faults. DBT'05: International Workshop on Current & Defect Based Testing, May 2005, Palm Springs, CA, United States. ⟨lirmm-00374937⟩
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