Electrical Analysis of a Domino Logic Cell with GOS Faults

Abstract : Gate-Oxide Shorts (GOS) have an increasing impact on the integrated circuit production yield due to the reduction of the related dimensions. The detection of GOS is a challenging issue in the field of testing. This paper presents a detailed study of the impact of a GOS fault affecting a Domino logic circuit. Indeed, Domino logic specific clocked operating principle induces a different behavior from standard full CMOS cells under the effect of a GOS, which can enable GOS detection. Finally, some clues to enhance GOS detection in Domino cells are proposed.
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Communication dans un congrès
DBT'05: International Workshop on Current & Defect Based Testing, May 2005, Palm Springs, CA, United States. 2005, 〈http://www.cs.colostate.edu/~malaiya/dbt05.html〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00374937
Contributeur : Mariane Comte <>
Soumis le : vendredi 10 avril 2009 - 13:09:01
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19
Document(s) archivé(s) le : jeudi 10 juin 2010 - 20:18:42

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Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell. Electrical Analysis of a Domino Logic Cell with GOS Faults. DBT'05: International Workshop on Current & Defect Based Testing, May 2005, Palm Springs, CA, United States. 2005, 〈http://www.cs.colostate.edu/~malaiya/dbt05.html〉. 〈lirmm-00374937〉

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