Simulating Resistive-Bridging and Stuck-At Faults - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Journal Articles IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Year : 2006

Simulating Resistive-Bridging and Stuck-At Faults

Piet Engelke
  • Function : Author
  • PersonId : 859548
Ilia Polian
  • Function : Author
  • PersonId : 859549
Bernd Becker
  • Function : Author
  • PersonId : 844529

Abstract

The authors present a simulator for resistive-bridging and stuck-at faults. In contrst to earlier work, it is based on electrical equations rather than table look up, thus, exposing more lexibility. For the first time, simulation of sequential circuits is dealt with; interation of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive-bridging and stuck-at faults in combinational and sequential circuits. Different definitions of coverage are listed, and quantitative results with respect to all these definitions are given for the first time.
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Dates and versions

lirmm-00375012 , version 1 (10-04-2009)

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Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker. Simulating Resistive-Bridging and Stuck-At Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25 (10), pp.2181-2192. ⟨10.1109/TCAD.2006.871626⟩. ⟨lirmm-00375012⟩
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