Simulating Resistive-Bridging and Stuck-At Faults

Piet Engelke 1 Ilia Polian 1 Michel Renovell 2 Bernd Becker 1
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : The authors present a simulator for resistive-bridging and stuck-at faults. In contrst to earlier work, it is based on electrical equations rather than table look up, thus, exposing more lexibility. For the first time, simulation of sequential circuits is dealt with; interation of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive-bridging and stuck-at faults in combinational and sequential circuits. Different definitions of coverage are listed, and quantitative results with respect to all these definitions are given for the first time.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00375012
Contributor : Mariane Comte <>
Submitted on : Friday, April 10, 2009 - 6:25:06 PM
Last modification on : Friday, July 20, 2018 - 12:34:01 PM

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Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker. Simulating Resistive-Bridging and Stuck-At Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2006, 25 (10), pp.2181-2192. ⟨lirmm-00375012⟩

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