Automatic Test Pattern Generation for Resistive Bridging Faults

Piet Engelke 1 Michel Renovell 2 Bernd Becker 1
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : An ATPG for resistive bridging faults in combinational or full-scan circuits is proposed. It combines the advantages of section-based generation and interval-based simulation. In contrast to the solutions introducted so far, it can handle static effects of arbitrary non-feedback bridges between two nodes, including ones detectable at higher bridge resistance and undetectable at lower resistance, and faults requiring more than one vector for detection. The developed tool is applied to ISCAS circuits, and a higher efficiency compared with other resistive bridging faults as well as stuck-at ATPG is reported. Information required for accurate resistive bridging fault simulation is obtained as a by-product.
Type de document :
Article dans une revue
Journal of Electronic Testing, Springer Verlag, 2006, 22 (1), pp.61-69
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00375014
Contributeur : Mariane Comte <>
Soumis le : vendredi 10 avril 2009 - 18:37:44
Dernière modification le : vendredi 20 juillet 2018 - 12:34:01

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  • HAL Id : lirmm-00375014, version 1

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Piet Engelke, Michel Renovell, Bernd Becker. Automatic Test Pattern Generation for Resistive Bridging Faults. Journal of Electronic Testing, Springer Verlag, 2006, 22 (1), pp.61-69. 〈lirmm-00375014〉

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