An Analysis of the Timing Behavior of CMOS Digital Blocks under Simultaneous Switching Noise Conditions

Florence Azaïs 1 Yves Bertrand 1 Michel Renovell 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper analyzes the impact of Simultaneous Switching Noise (SSN) on the timing behavior of CMOS digital blocks. The concept of Instantaneous Transfer Function is introduced to interpret noisy signals and perform timing measurements on such signals. It is shown that the average swing during switching is the key parameter to predict the noise impact on the delay of a logic path, whereas the peak of noise is not relevant. The influence of structural parameters such as the block topology is evaluated, and the unpredictable aspect of SSN impact on path delay is highlighted.
Type de document :
Communication dans un congrès
DDECS'09: IEEE Design and Diagnostics of Electronic Circuits and Systems, Apr 2009, Liberec, Czech Republic. pp.158-163, 2009
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00386906
Contributeur : Florence Azais <>
Soumis le : vendredi 22 mai 2009 - 11:21:01
Dernière modification le : vendredi 20 juillet 2018 - 12:34:01

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  • HAL Id : lirmm-00386906, version 1

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Florence Azaïs, Yves Bertrand, Michel Renovell. An Analysis of the Timing Behavior of CMOS Digital Blocks under Simultaneous Switching Noise Conditions. DDECS'09: IEEE Design and Diagnostics of Electronic Circuits and Systems, Apr 2009, Liberec, Czech Republic. pp.158-163, 2009. 〈lirmm-00386906〉

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