Using TMR Architectures for SoC Yield Improvement - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2009
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lirmm-00406967 , version 1 (23-07-2009)

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  • HAL Id : lirmm-00406967 , version 1

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Julien Vial, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Using TMR Architectures for SoC Yield Improvement. VALID'09: The First International Conference on Advances in System Testing and Validation Lifecycle, 2009, Porto, Portugal. pp.155-160. ⟨lirmm-00406967⟩
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