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Conference Papers Year : 2009

Using TMR Architectures for SoC Yield Improvement

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Micro and nanotechnologies/Microelectronics

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00406967

Submitted on : Thursday, July 23, 2009-5:26:06 PM

Last modification on : Friday, March 24, 2023-2:52:52 PM

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lirmm-00406967 , version 1 (23-07-2009)

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  • HAL Id : lirmm-00406967 , version 1

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Julien Vial, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Using TMR Architectures for SoC Yield Improvement. VALID'09: The First International Conference on Advances in System Testing and Validation Lifecycle, 2009, Porto, Portugal. pp.155-160. ⟨lirmm-00406967⟩

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