Delay Fault Diagnosis in Sequential Circuits

Abstract : The importance of delay faults proportionally increases when entering in the nano-technology era, and logic diagnosis must localize delay faults as precisely as possible to speed-up yield ramp-up. This paper presents a logic diagnosis approach targeting delay faults. The proposed approach is based on the single-location-at-a-time (SLAT) paradigm used to determine a set of suspects. It addresses the case of sequential circuits tested at-speed. The main advantages of this approach are that it can manage a comprehensive set of delay faults, and that it is independent on the size of the delay (induced by the fault). Experimental results show the effectiveness of the proposed approach in terms of absolute number of suspects.
Type de document :
Communication dans un congrès
ATS: Asian Test Symposium, Nov 2009, Taichung, Taiwan. 18th IEEE Asian Test Symposium, pp.355-360, 2009
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00406968
Contributeur : Lionel Torres <>
Soumis le : jeudi 23 juillet 2009 - 17:29:35
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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  • HAL Id : lirmm-00406968, version 1

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Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Delay Fault Diagnosis in Sequential Circuits. ATS: Asian Test Symposium, Nov 2009, Taichung, Taiwan. 18th IEEE Asian Test Symposium, pp.355-360, 2009. 〈lirmm-00406968〉

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