On-Chip Timing Slack Monitoring

Abstract : PVT monitors are mandatory to use tunable knobs designed to compensate the variability effects. This paper de-scribes a new on-chip monitoring system, allowing failure antici-pation in real-time, in looking at the timing slack of a pre-defined set of observable flip-flops. This system is made of special struc-tures situated near the flip-flops, coupled with a specific detection window generator, embedded within the clock-tree. Validation and performances simulated in a 45 nm technology demonstrate a scalable, low power and low area fine-grain system, easily in-sertable in a standard CAD flow.
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Communication dans un congrès
VLSI-SOC 2009: IFIP/IEEE International Conference on Very Large Scale Integration, Oct 2009, Florianopolis, Brazil. pp.89-94, 2009, Session: Physical Design, Low Power Design. 〈10.1109/VLSISOC.2009.6041336〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00429350
Contributeur : Isabelle Gouat <>
Soumis le : lundi 2 novembre 2009 - 15:52:09
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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Bettina Rebaud, Marc Belleville, Edith Beigne, Michel Robert, Philippe Maurine, et al.. On-Chip Timing Slack Monitoring. VLSI-SOC 2009: IFIP/IEEE International Conference on Very Large Scale Integration, Oct 2009, Florianopolis, Brazil. pp.89-94, 2009, Session: Physical Design, Low Power Design. 〈10.1109/VLSISOC.2009.6041336〉. 〈lirmm-00429350〉

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