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On-Chip Timing Slack Monitoring

Abstract : PVT monitors are mandatory to use tunable knobs designed to compensate the variability effects. This paper de-scribes a new on-chip monitoring system, allowing failure antici-pation in real-time, in looking at the timing slack of a pre-defined set of observable flip-flops. This system is made of special struc-tures situated near the flip-flops, coupled with a specific detection window generator, embedded within the clock-tree. Validation and performances simulated in a 45 nm technology demonstrate a scalable, low power and low area fine-grain system, easily in-sertable in a standard CAD flow.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00429350
Contributor : Isabelle Gouat <>
Submitted on : Monday, November 2, 2009 - 3:52:09 PM
Last modification on : Thursday, June 11, 2020 - 5:04:06 PM

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Bettina Rebaud, Marc Belleville, Edith Beigné, Michel Robert, Philippe Maurine, et al.. On-Chip Timing Slack Monitoring. VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2009, Florianopolis, Brazil. pp.89-94, ⟨10.1109/VLSISOC.2009.6041336⟩. ⟨lirmm-00429350⟩

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