Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of Variabilities

Abstract : PVT information is mandatory to control specific knobs to compen-sate the variability effects. In this paper, we propose a new on-chip monitoring system and its associated integration flow, allowing timing failure anticipation in real-time, observing the timing slack of a pre-defined set of observable flip-flops. This system is made of specific structures located nearby the flip-flops, coupled with a detection window generator, embedded within the clock-tree. Validation and performances simulated in a 45 nm technology demonstrate a scalable, low power and low area, fine-grain system. The integration flow re-sults exhibit the weak impact of the insertion of this monitoring system toward the large benefits of tuning the circuit at its optimum working point.
Type de document :
Communication dans un congrès
Patmos'09: 19th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2009, Delft, Netherlands. Springer, pp.266-275, 2009
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00433462
Contributeur : Nadine Azemard <>
Soumis le : jeudi 19 novembre 2009 - 14:19:55
Dernière modification le : mercredi 24 octobre 2018 - 09:02:05

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  • HAL Id : lirmm-00433462, version 1

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Bettina Rebaud, Marc Belleville, Edith Beigne, Christian Bernard, Michel Robert, et al.. Digital Timing Slack Monitors and their Specific Insertion Flow for Adaptive Compensation of Variabilities. Patmos'09: 19th International Workshop on Power and Timing Modeling Optimization and Simulation, Sep 2009, Delft, Netherlands. Springer, pp.266-275, 2009. 〈lirmm-00433462〉

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