Statistical Static Timing Analysis (SSTA) is becoming necessary; but has not been widely adopted. One of those arguments against the use is that results of SSTA are difficult to make use of for circuit design. In this paper, by introducing conditional moments, we propose a path-based statistical timing approach, which permits us to consider gate topology and switching process in-duced correlations. With the help of this gate-to-gate delay correlation, differ-ences between results of SSTA and those of Worst-case Timing Analysis (WTA) are interpreted. Numerical results demonstrate that path delay means and standard deviations estimated by the proposed approach have absolute val-ues of relative errors respectively less than 5% and 10%.