With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. To address this problem during SoC development, memory cores are built with hardware redundancies. On the other hand, logic cores embedded in SoC usually do not have such redundancy capabilities. Therefore, manufacturing defects affecting these cores decrease the yield of the entire SoC. Consequently, meaningful techniques for SoC yield improvement must also consider logic cores. In this paper, we propose and investigate the usage of TMR architectures for logic cores to increase the overall SoC yield. In order to analyze the TMR effectiveness, we resort to two defects distribution models, the Poisson and negative binomial distributions, that are also compared. Results obtained on SoC examples demonstrate the interest of using TMR architectures for SoC yield enhancement purpose.