Yes, we Can Improve SoC Yield

Abstract : With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. To address this problem during SoC development, memory cores are built with hardware redundancies. On the other hand, logic cores embedded in SoC usually do not have such redundancy capabilities. Therefore, manufacturing defects affecting these cores decrease the yield of the entire SoC. Consequently, meaningful techniques for SoC yield improvement must also consider logic cores. In this paper, we propose and investigate the usage of TMR architectures for logic cores to increase the overall SoC yield. In order to analyze the TMR effectiveness, we resort to two defects distribution models, the Poisson and negative binomial distributions, that are also compared. Results obtained on SoC examples demonstrate the interest of using TMR architectures for SoC yield enhancement purpose.
Type de document :
Communication dans un congrès
PRIME'09: Conference on Ph.D. Research in Microelectronics and Electronics, pp.272-275, 2009
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00433763
Contributeur : Arnaud Virazel <>
Soumis le : vendredi 20 novembre 2009 - 10:38:32
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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  • HAL Id : lirmm-00433763, version 1

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Julien Vial, Arnaud Virazel. Yes, we Can Improve SoC Yield. PRIME'09: Conference on Ph.D. Research in Microelectronics and Electronics, pp.272-275, 2009. 〈lirmm-00433763〉

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