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Conference Poster Year : 2009

A Logic Diagnosis Approach for Sequential Circuits

Abstract

This paper presents a logic diagnosis approach targeting sequential circuit performed in two phases, (i) a fault localization phase searching in to the dictionary a set of suspected lines able to explain the observed errors, and (ii) a fault model allocation phase associating a set of fault models on each suspect identified in the first phase. The main advantages of this approach are that the fault localization phase is fault model independent, and that the fault model allocation phase is able to deal with several fault models at a time (static and dynamic).
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Dates and versions

lirmm-00433792 , version 1 (20-11-2009)

Identifiers

  • HAL Id : lirmm-00433792 , version 1

Cite

Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. A Logic Diagnosis Approach for Sequential Circuits. ETS 2009 - 14th IEEE European Test Symposium, May 2009, Sevilla, Spain. , 2009, Ph. D. Forum. ⟨lirmm-00433792⟩
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