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Poster communications

A Logic Diagnosis Approach for Sequential Circuits

Abstract : This paper presents a logic diagnosis approach targeting sequential circuit performed in two phases, (i) a fault localization phase searching in to the dictionary a set of suspected lines able to explain the observed errors, and (ii) a fault model allocation phase associating a set of fault models on each suspect identified in the first phase. The main advantages of this approach are that the fault localization phase is fault model independent, and that the fault model allocation phase is able to deal with several fault models at a time (static and dynamic).
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Poster communications
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00433792
Contributor : Alberto Bosio <>
Submitted on : Friday, November 20, 2009 - 10:49:23 AM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM

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  • HAL Id : lirmm-00433792, version 1

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Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. A Logic Diagnosis Approach for Sequential Circuits. IEEE European Test Symposium'09, Ph. D. Forum, Spain. 2009. ⟨lirmm-00433792⟩

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