SoC Yield Improvement for Future Nanoscale Technologies

Abstract : Manufacturing processes in the nanoscale era are less and less reliable thus leading to lower and lower yield. In this paper we investigate the usage of TMR (Triple Modular Redundancy), a fault tolerant architecture, for logic cores to increase their manufacturing yield and thus raise the overall SoC yield.
Type de document :
Poster
European Test Symposium. PhD Forum, Spain. 2009
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00433798
Contributeur : Arnaud Virazel <>
Soumis le : vendredi 20 novembre 2009 - 10:54:24
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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  • HAL Id : lirmm-00433798, version 1

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Julien Vial, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. SoC Yield Improvement for Future Nanoscale Technologies. European Test Symposium. PhD Forum, Spain. 2009. 〈lirmm-00433798〉

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