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Conference Poster Year : 2009

SoC Yield Improvement for Future Nanoscale Technologies

Abstract

Manufacturing processes in the nanoscale era are less and less reliable thus leading to lower and lower yield. In this paper we investigate the usage of TMR (Triple Modular Redundancy), a fault tolerant architecture, for logic cores to increase their manufacturing yield and thus raise the overall SoC yield.
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Dates and versions

lirmm-00433798 , version 1 (20-11-2009)

Identifiers

  • HAL Id : lirmm-00433798 , version 1

Cite

Julien Vial, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. SoC Yield Improvement for Future Nanoscale Technologies. ETS 2009 - 14th IEEE European Test Symposium | PhD Forum, May 2009, Sevilla, Spain. 2009. ⟨lirmm-00433798⟩
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