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Poster communications

SoC Yield Improvement for Future Nanoscale Technologies

Abstract : Manufacturing processes in the nanoscale era are less and less reliable thus leading to lower and lower yield. In this paper we investigate the usage of TMR (Triple Modular Redundancy), a fault tolerant architecture, for logic cores to increase their manufacturing yield and thus raise the overall SoC yield.
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Poster communications
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Contributor : Arnaud Virazel <>
Submitted on : Friday, November 20, 2009 - 10:54:24 AM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM


  • HAL Id : lirmm-00433798, version 1



Julien Vial, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. SoC Yield Improvement for Future Nanoscale Technologies. European Test Symposium. PhD Forum, Spain. 2009. ⟨lirmm-00433798⟩



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