Fast Digital Post-Processing Technique for INL Correction of ADC: Validation on a 12-bit Folding-and-Interpolating Analog-to-Digital Converter

Abstract : The semiconductor industry tends to constantly increase the performances of developed systems with an ever-shorter time-to-market. In this context, the conventional strategy for mixed-signal component design, which is based only on analog design effort, will no longer be suitable. In this paper, a digital correction technique is presented for Analog-to-Digital Converters (ADC). The idea is to use a Look-Up-Table (LUT) for the online correction of Integral Non-Linearity (INL). The main challenge for this kind of technique is the cost in time and resources to estimate the actual INL of the ADC needed to load the LUT. In this paper we propose to extract INL with a very rapid procedure based on spectral analysis. We validate our technique on a 12-bit Folding-and-Interpolating ADC and we demonstrate that the correction is efficient for a large range of application fields.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00506494
Contributor : Serge Bernard <>
Submitted on : Wednesday, July 28, 2010 - 12:59:39 AM
Last modification on : Wednesday, August 28, 2019 - 7:12:02 PM

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  • HAL Id : lirmm-00506494, version 1

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Vincent Kerzérho, Vincent Fresnaud, Dominique Dallet, Serge Bernard, Lilian Bossuet. Fast Digital Post-Processing Technique for INL Correction of ADC: Validation on a 12-bit Folding-and-Interpolating Analog-to-Digital Converter. IEEE Transactions on Instrumentation and Measurement, Institute of Electrical and Electronics Engineers, 2011, 60, pp.768-775. ⟨lirmm-00506494⟩

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