Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPC

Abstract : This paper aims at introducing a safe voltage scaling and body biasing methodology for Low-Density Parity Check (LDPC) hard-wired IP. The proposed methodology allows an efficient post-silicon tuning of the LDPC, and the performances can be adapted to High Speed mode, or Low Operating Power mode, or Low Standby Power mode requirements. Concrete 45nm silicon results are introduced in this paper to demonstrate the added value of the methodology. More precisely, it is shown that running the High Performance mode leads to +24% on circuit maximum operating frequency. And the Low Standby Power mode results on x0.73 leakage minimization. The proposed adaptive LDPC encoder/decoder can remove some barriers to the adoption of long LDPC codes on portable devices.
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Communication dans un congrès
ICICDT'10: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.N/A, 2010
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00546316
Contributeur : Nadine Azemard <>
Soumis le : mardi 14 décembre 2010 - 10:34:48
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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  • HAL Id : lirmm-00546316, version 1

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Nabila Moubdi, Philippe Maurine, Nadine Azemard, Robin Wilson, Sylvain Engels. Voltage Scaling and Body Biasing Methodology for High Performance Hardwired LDPC. ICICDT'10: International Conference on Integrated Circuit Design & Technology, Jun 2010, Grenoble, France. pp.N/A, 2010. 〈lirmm-00546316〉

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