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Conference Papers Year : 2010

Providing Better Multi-Processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism

Abstract

In this paper we propose a strategy for better ex- ploiting Multi-Processor Systems-on-Chip resources utilization by means of using a control-loop feedback mechanism. We apply the proposed techniques in a purely distributed memory MPSoC architecture that is composed of a frequency scaling module responsible for tuning the frequency of processors at run-time. Results show very promising in terms of adaptation capabilities for system with dynamic workload. Performance results demonstrate the effectiveness of the proposed approach when workload requirements for applications may vary, af- fecting the overall performance of the system. For validating the proposed approach we have implemented a multi-thread MJPEG decoder application and created an architecture model with/without perturbations in the system.
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Dates and versions

lirmm-00548837 , version 1 (30-06-2022)

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Gabriel Marchesan Almeida, Remi Busseuil, Sameer Varyani, Nicolas Hébert, Gilles Sassatelli, et al.. Providing Better Multi-Processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism. ReConFig 2010 - International Conference on ReConFigurable Computing and FPGAs, Dec 2010, Cancun, Mexico. pp.382-387, ⟨10.1109/ReConFig.2010.17⟩. ⟨lirmm-00548837⟩
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