Ultra Compact Non-Volatile Flip-Flop for Low-Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2011

Ultra Compact Non-Volatile Flip-Flop for Low-Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology

Abstract

Complex systems are mainly integrated in CMOS technology, facing issues in advanced process nodes, in particular for power consumption and heat dissipation. Magnetic devices such as Magnetic Tunnel Junction (MTJ) have specific features: non-volatility, high cyclability (over 1016) and immunity to radiations. Combined with CMOS devices they offer specific and new features to designs. Indeed, the emerging hybrid CMOS/Magnetic process allows integrating magnetic devices within digital circuits, modifying the current architectures, in order to contribute to solve the CMOS process issues. We present a high performance innovative non-volatile latch integrated into a flip-flop which can operate at high speed. It can be used to design non-volatile logic circuits with ultra low-power consumption and new functionalities such as instant startup. This new flip-flop is integrated as a standard cell in a full Magnetic Process Design Kit (MPDK) allowing full custom and digital design of hybrid CMOS/Magnetic circuits using standard design tools.
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lirmm-00616949 , version 1 (14-09-2019)

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Gregory Di Pendina, Guillaune Prenat, Khouldoun Torki, Yoann Guillemenet, Lionel Torres. Ultra Compact Non-Volatile Flip-Flop for Low-Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology. PATMOS 2011 - 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, Sep 2011, Madrid, Spain. pp.83-91, ⟨10.1007/978-3-642-24154-3_9⟩. ⟨lirmm-00616949⟩
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