Ultra Compact Non-Volatile Flip-Flop for Low-Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology

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Communication dans un congrès
PATMOS'11: 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, Sep 2011, Madrid, Spain. Springer, 6951, pp.83-91, 2011, Lecture note in Computer Science. 〈http://patmos.dacya.ucm.es/〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00616949
Contributeur : Lionel Torres <>
Soumis le : jeudi 25 août 2011 - 11:05:17
Dernière modification le : vendredi 19 octobre 2018 - 20:44:01

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  • HAL Id : lirmm-00616949, version 1

Citation

Gregory Di Pendina, Guillaune Prenat, Khouldoun Torki, Yoann Guillemenet, Lionel Torres. Ultra Compact Non-Volatile Flip-Flop for Low-Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology. PATMOS'11: 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, Sep 2011, Madrid, Spain. Springer, 6951, pp.83-91, 2011, Lecture note in Computer Science. 〈http://patmos.dacya.ucm.es/〉. 〈lirmm-00616949〉

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