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A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits Parity Prediction Synthesis for Nano-Electronic Gate Designs

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00651238
Contributor : Martine Peridier <>
Submitted on : Tuesday, December 13, 2011 - 11:01:08 AM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM

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  • HAL Id : lirmm-00651238, version 1

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Ahn Duc Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits Parity Prediction Synthesis for Nano-Electronic Gate Designs. ATS: Asian Test Symposium, Nov 2011, New Delhi, India. pp.136-141. ⟨lirmm-00651238⟩

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