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Power-Aware Test Pattern Generation for At-Speed LOS Testing

Alberto Bosio 1 Luigi Dilillo 1 Patrick Girard 1 Aida Todri-Sanial 1 Arnaud Virazel 1 Kohei Miyase 2 Xiaoqing Wen 2 
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Launch-off-Capture (LOC) and Launch-off-Shift (LOS) are the two main test schemes for at-speed scan delay testing. In the literature, it has been shown that LOS has higher performance than LOC in terms of fault coverage and test length, but higher peak power consumption during the launch-to-capture cycle. Power reduction seems to be the key to really exploit LOS test scheme. However, it has been proven that reducing too much test power can lead to test escape due to under-test. In this context, this study proposes a smart X-filling framework able to adapt peak power consumption during the launch-to-capture cycle according to the functional power, i.e. the power consumption of the circuit in functional mode. Here, the main goal is to obtain a final test set with peak power consumption as close as possible to the functional power. Experimental results, carried out on the well-known ITC'99 benchmarks, prove the feasibility of the proposed approach.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00651917
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Submitted on : Wednesday, December 14, 2011 - 3:07:38 PM
Last modification on : Friday, August 5, 2022 - 10:48:04 AM

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  • HAL Id : lirmm-00651917, version 1

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Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, et al.. Power-Aware Test Pattern Generation for At-Speed LOS Testing. ATS: Asian Test Symposium, Nov 2011, New Delhi, India. pp.506-510. ⟨lirmm-00651917⟩

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