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On-Chip Comparison for Testing Secure ICs

Jean da Rolt 1 Giorgio Di Natale 1 Marie-Lise Flottes 1 Bruno Rouzeyre 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Hardware implement ations of secure applications, e.g. cryptographic algorithms, are subject to various attacks. In particular, it has been demonstrated that scan chains introduced by Design for Testability open a backdoor to potential attacks. In this paper we propose a scan protection scheme that provides testing facilities both at production time and during the circuit's lifetime . The underlying principle is to scan-in both input vectors and expected responses, and to perform the comparison between expected and actual responses within the circuit. Compared to regular scan test, this technique has no impact on test quality and no impact on diagnostic of modeled faults . It entails a negligible area overhead and it avoids the use of an authentication test mechanism
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Submitted on : Wednesday, February 27, 2013 - 3:40:18 PM
Last modification on : Tuesday, September 1, 2020 - 11:32:04 AM
Long-term archiving on: : Tuesday, May 28, 2013 - 6:40:07 AM


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  • HAL Id : lirmm-00795205, version 1



Jean da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On-Chip Comparison for Testing Secure ICs. DCIS'2012: Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.112-117. ⟨lirmm-00795205⟩



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