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Conference Papers Year : 2012

On-Chip Comparison for Testing Secure ICs

Abstract

Hardware implement ations of secure applications, e.g. cryptographic algorithms, are subject to various attacks. In particular, it has been demonstrated that scan chains introduced by Design for Testability open a backdoor to potential attacks. In this paper we propose a scan protection scheme that provides testing facilities both at production time and during the circuit's lifetime . The underlying principle is to scan-in both input vectors and expected responses, and to perform the comparison between expected and actual responses within the circuit. Compared to regular scan test, this technique has no impact on test quality and no impact on diagnostic of modeled faults . It entails a negligible area overhead and it avoids the use of an authentication test mechanism
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Dates and versions

lirmm-00795205 , version 1 (27-02-2013)

Identifiers

  • HAL Id : lirmm-00795205 , version 1

Cite

Jean da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On-Chip Comparison for Testing Secure ICs. DCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.112-117. ⟨lirmm-00795205⟩
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