Skip to Main content Skip to Navigation
Journal articles

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes

Renan Alves Fonseca 1 Luigi Dilillo 1, * Alberto Bosio 1 Patrick Girard 1 Serge Pravossoudovitch 1 Arnaud Virazel 1 Nabil Badereddine 2
* Corresponding author
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 Intel Mobile
IMC - Intel Mobile Communications
Abstract : We present a study on the effects of resistive-bridging defects in the SRAM core-cell, considering different industrial technology nodes: 90 nm, 65 nm and 40 nm. We have performed an extensive number of electrical simulations, varying the resistance value of the defects, the supply voltage, the memory size and the temperature. We identified the worst-case conditions maximizing failure occurrence in presence of defects. Results also show that resistive-bridging defects cause malfunction in the defective core-cell, as well as in non-defective core-cells located in the same row and/or column. Moreover, the weak read fault is the fault that is the most likely to occur due to resistive-bridging defects. Finally, the sensitivity of SRAMs to resistive-bridging defects increases with the advance of technology nodes.
Document type :
Journal articles
Complete list of metadata
Contributor : Luigi Dilillo <>
Submitted on : Tuesday, March 26, 2013 - 6:48:04 PM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM

Links full text




Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. Journal of Electronic Testing, Springer Verlag, 2012, 28 (3), pp.317-329. ⟨10.1007/s10836-012-5291-6⟩. ⟨lirmm-00805017⟩



Record views