Failure Analysis and Test Solutions for Low-Power SRAMs

Abstract : Low-power SRAMs embed power gating facilities for reducing power consumption. Power gating is applied using power switches for controlling the supply voltage applied to the memory cells i.e. one or more memory blocks can be disconnected from the power supply during a long time of inactivity, thus reducing the power consumption. In this paper, we provide a detailed analysis on the impact that defective power switches impose on the behavior of SRAM core-cells. Furthermore, we propose efficient test solutions to detect such faulty behaviors.
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Communication dans un congrès
ATS: Asian Test Symposium, Nov 2011, New Delhi, India. 20th IEEE Asian Test Symposium, pp.459-460, 2011, 〈http://www.ecs.umass.edu/ece/ats11/〉. 〈10.1109/ATS.2011.97〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00805123
Contributeur : Luigi Dilillo <>
Soumis le : mercredi 27 mars 2013 - 10:29:10
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Failure Analysis and Test Solutions for Low-Power SRAMs. ATS: Asian Test Symposium, Nov 2011, New Delhi, India. 20th IEEE Asian Test Symposium, pp.459-460, 2011, 〈http://www.ecs.umass.edu/ece/ats11/〉. 〈10.1109/ATS.2011.97〉. 〈lirmm-00805123〉

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