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Failure Analysis and Test Solutions for Low-Power SRAMs

Leonardo B. Zordan 1 Alberto Bosio 1 Luigi Dilillo 1 Patrick Girard 1 Serge Pravossoudovitch 1 Aida Todri-Sanial 1 Arnaud Virazel 1 Nabil Badereddine 2
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 IMC - Intel Mobile Communications
Abstract : Low-power SRAMs embed power gating facilities for reducing power consumption. Power gating is applied using power switches for controlling the supply voltage applied to the memory cells i.e. one or more memory blocks can be disconnected from the power supply during a long time of inactivity, thus reducing the power consumption. In this paper, we provide a detailed analysis on the impact that defective power switches impose on the behavior of SRAM core-cells. Furthermore, we propose efficient test solutions to detect such faulty behaviors.
Keywords : power switch failure analysis low-power design memory test SRAM
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Conference papers
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00805123
Contributor : Luigi Dilillo <>
Submitted on : Wednesday, March 27, 2013 - 10:29:10 AM
Last modification on : Wednesday, December 11, 2019 - 1:32:02 AM

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CNRS | SYSMIC | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER

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Leonardo B. Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, et al.. Failure Analysis and Test Solutions for Low-Power SRAMs. ATS: Asian Test Symposium, Nov 2011, New Delhi, India. pp.459-460, ⟨10.1109/ATS.2011.97⟩. ⟨lirmm-00805123⟩

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