Low-power SRAMs Power Mode Control Logic: Failure Analysis and Test Solutions

Leonardo Zordan 1 Alberto Bosio 1 Luigi Dilillo 1 Patrick Girard 1 Aida Todri 1 Arnaud Virazel 1 Nabil Badereddine 2
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 Intel Mobile
IMC - Intel Mobile Communications
Abstract : Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is implemented through power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This way, one or more memory blocks can be disconnected from the power supply during a long period of inactivity, thus reducing static power consumption. This paper focuses on low-power SRAMs, and in particular, the power gating mechanisms of core-cells and peripheral circuitry. We provide a detailed analysis based on electrical simulations to characterize the impact of resistive-open defects on the power mode control logic. Based on this analysis, we introduce appropriate fault models that represent the observed faulty behaviors. Finally, we propose an efficient test solution targeting the set of identified fault models.
Type de document :
Communication dans un congrès
ITC'2012: International Test Conference, Nov 2012, Anaheim, CA, United States. IEEE, pp.1-10, 2012, 〈http://www.itctestweek.org/〉. 〈10.1109/TEST.2012.6401578〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00805143
Contributeur : Luigi Dilillo <>
Soumis le : mercredi 27 mars 2013 - 11:04:21
Dernière modification le : vendredi 2 mars 2018 - 19:36:02

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Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, et al.. Low-power SRAMs Power Mode Control Logic: Failure Analysis and Test Solutions. ITC'2012: International Test Conference, Nov 2012, Anaheim, CA, United States. IEEE, pp.1-10, 2012, 〈http://www.itctestweek.org/〉. 〈10.1109/TEST.2012.6401578〉. 〈lirmm-00805143〉

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