Low-power SRAMs Power Mode Control Logic: Failure Analysis and Test Solutions - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2012

Low-power SRAMs Power Mode Control Logic: Failure Analysis and Test Solutions

Abstract

Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is implemented through power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This way, one or more memory blocks can be disconnected from the power supply during a long period of inactivity, thus reducing static power consumption. This paper focuses on low-power SRAMs, and in particular, the power gating mechanisms of core-cells and peripheral circuitry. We provide a detailed analysis based on electrical simulations to characterize the impact of resistive-open defects on the power mode control logic. Based on this analysis, we introduce appropriate fault models that represent the observed faulty behaviors. Finally, we propose an efficient test solution targeting the set of identified fault models.
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Dates and versions

lirmm-00805143 , version 1 (27-03-2013)

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Cite

Leonardo B. Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Low-power SRAMs Power Mode Control Logic: Failure Analysis and Test Solutions. ITC'2012: International Test Conference, Nov 2012, Anaheim, CA, United States. pp.1-10, ⟨10.1109/TEST.2012.6401578⟩. ⟨lirmm-00805143⟩
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