Defect Analysis in Power Mode Control Logic of Low-Power SRAMs

Abstract : Summary form only given. Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is applied in SRAMs using power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This paper provides a detailed analysis based on electrical simulations to describe the impacts of resistive-open defects on the power mode control logic, which generates control signals of power switches.
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Communication dans un congrès
ETS: European Test symposium, May 2012, Annecy, France. 17th IEEE European Test Symposium, 2012, 〈http://ets2012.imag.fr/〉. 〈10.1109/ETS.2012.6233033〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00805374
Contributeur : Luigi Dilillo <>
Soumis le : mercredi 27 mars 2013 - 17:38:19
Dernière modification le : mardi 25 septembre 2018 - 14:30:02

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Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Defect Analysis in Power Mode Control Logic of Low-Power SRAMs. ETS: European Test symposium, May 2012, Annecy, France. 17th IEEE European Test Symposium, 2012, 〈http://ets2012.imag.fr/〉. 〈10.1109/ETS.2012.6233033〉. 〈lirmm-00805374〉

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