Peak Power Estimation: A Case Study on CPU Cores

Abstract : High peak power consumption during test may lead to yield loss. On the other hand, reducing too much test power may lead to test escape. In order to overcome this problem, test power has to mimic the power consumed during functional mode, being as high as possible but not crossing the frontier of over-consumption. Measuring power consumption is a very time consuming activity, therefore many works in the literature focused on the indirect ways to provide power consumption estimation in a fast manner. In this paper we concentrate on a similar issue, concentrating our effort on devising a fast method for the identification and estimation of the peak power produced by test patterns. In particular we provide a detailed discussion on case studies related to peak power estimation of CPU cores when executing functional patterns, the proposed method uses the gate-level description of the CPU to identify a subset of time points over the entire test pattern that are showing the most significant peak power values. The proposed methodology has been validated on two case studies synthesized in a 65nm industrial technology.
Type de document :
Communication dans un congrès
IEEE Asian Test Symposium, Nov 2012, Niigata, Japan. IEEE, pp.167-172, 2012, 〈http://aries3a.cse.kyutech.ac.jp/~ats12/〉. 〈10.1109/ATS.2012.58〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00805389
Contributeur : Luigi Dilillo <>
Soumis le : mercredi 27 mars 2013 - 18:21:08
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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Paolo Bernardi, Mauricio De Carvalho, Ernesto Sanchez, Matteo Sonza Reorda, Alberto Bosio, et al.. Peak Power Estimation: A Case Study on CPU Cores. IEEE Asian Test Symposium, Nov 2012, Niigata, Japan. IEEE, pp.167-172, 2012, 〈http://aries3a.cse.kyutech.ac.jp/~ats12/〉. 〈10.1109/ATS.2012.58〉. 〈lirmm-00805389〉

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