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A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant Architectures

Abstract : Although CMOS technology scaling offers many advantages, it suffers from robustness problem caused by hard, soft and timing errors. The robustness of future CMOS technology nodes must be improved and the use of fault tolerant architectures is probably the most viable solution. In this context, Duplication/Comparison scheme is widely used for error detection. Traditionally, this scheme uses a static comparator structure that detects hard error. However, it is not effective for soft and timing errors detection due to the possible masking of glitches by the comparator itself. To solve this problem, we propose a pseudo-dynamic comparator architecture that combines a dynamic CMOS transition detector and a static comparator. Experimental results show that the proposed comparator detects not only hard errors but also small glitches related to soft and timing errors. Moreover, its dynamic characteristics allow reducing the power consumption while keeping an equivalent silicon area compared to a static comparator. This study is the first step towards a full fault tolerant approach targeting robustness improvement of CMOS logic circuits.
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Contributor : Arnaud Virazel <>
Submitted on : Tuesday, April 2, 2013 - 12:30:38 PM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM




Ahn Duc Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. A Pseudo-Dynamic Comparator for Error Detection in Fault Tolerant Architectures. VTS: VLSI Test Symposium, Apr 2012, Hawaii, United States. pp.50-55, ⟨10.1109/VTS.2012.6231079⟩. ⟨lirmm-00806778⟩



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