Three-dimensional (3D) integration is a fast emerging technology that offers integration of high density, fast performance and heterogeneous circuits in a small footprint. Through-Silicon-Vias (TSVs) enable 3D integration by providing fast performance and short interconnects among tiers. However, they are also susceptible to defects that occur during manufacturing steps and cause crucial reliability issues. In this paper, we perform an in-depth analysis of resistive-open defects (ROD) on TSVs for various scenarios. We consider TSV ROD analysis in the presence of voltage drop, ground bounce, and coupling effects (i.e. inductive and capacitive) for a wide frequency spectrum. We perform a study on a three-tier structure and demonstrate conditions in which TSVs start to fail. Furthermore, we show the impact that the electrical behavior of the multi-tier network has on TSV performance.