Through-Silicon-Via Resistive-Open Defect Analysis - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2012

Through-Silicon-Via Resistive-Open Defect Analysis


Three-dimensional (3D) integration is a fast emerging technology that offers integration of high density, fast performance and heterogeneous circuits in a small footprint. Through-Silicon-Vias (TSVs) enable 3D integration by providing fast performance and short interconnects among tiers. However, they are also susceptible to defects that occur during manufacturing steps and cause crucial reliability issues. In this paper, we perform an analysis of resistive-open defects (ROD) on TSVs considering coupling effects (i.e. inductive and capacitive) and a wide frequency spectrum. Our experiments show that both substrate coupling and switching frequency can have a significant impact on weak open TSV behavior.
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lirmm-00806848 , version 1 (02-04-2013)



Carolina Momo Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Through-Silicon-Via Resistive-Open Defect Analysis. ETS: European Test Symposium, May 2012, Annecy, France. ⟨10.1109/ETS.2012.6233037⟩. ⟨lirmm-00806848⟩
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