Improving Defect Localization Accuracy by means of Effect-Cause Intra-Cell Diagnosis at Transistor Level

Abstract : Logic diagnosis is the process of isolating possible sources of observed errors in a defective circuit, so that physical failure analysis can be performed to determine the root cause of such errors. Thus, effective and accurate logic diagnosis is crucial to speed up physical failure analysis process and eventually to improve the yield. In this paper, we propose a new intra-cell diagnosis method based on the "Effect-Cause" approach to improve the defect localization accuracy. The proposed approach is based on the Critical Path Tracing here applied at transistor level. It leads to a more precise localization of the root cause of observed errors compared to state-of-the-art diagnosis approaches. Experimental results show the efficiency of our approach.
Type de document :
Communication dans un congrès
SDD: Silicon Debug and Diagnosis, Sep 2013, Anaheim, CA, United States. 8th IEEE International Workshop on Silicon Debug and Diagnosis, 2013, 〈http://sdd.tttc-events.org/13/〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00806872
Contributeur : Alberto Bosio <>
Soumis le : mardi 2 avril 2013 - 15:04:40
Dernière modification le : mardi 25 septembre 2018 - 14:30:02

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  • HAL Id : lirmm-00806872, version 1

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Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, et al.. Improving Defect Localization Accuracy by means of Effect-Cause Intra-Cell Diagnosis at Transistor Level. SDD: Silicon Debug and Diagnosis, Sep 2013, Anaheim, CA, United States. 8th IEEE International Workshop on Silicon Debug and Diagnosis, 2013, 〈http://sdd.tttc-events.org/13/〉. 〈lirmm-00806872〉

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