SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration

Florian Devic 1 Lionel Torres 2 Jérémie Crenne 3 Benoit Badrignans 4 Pascal Benoit 2
1 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
3 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance [Lorient]
4 NETHEOS - NETHEOS
Abstract : Dynamic partial reconfiguration is a growing need for SRAM FPGA-based embedded systems. This feature allows reconfiguring parts of the FPGA while others continue to run. But it may introduce security breaches affecting FPGA configuration. In this paper, a secure protocol to ensure confidentiality, integrity, authenticity and up-to-dateness is described and applied to dynamic partial reconfiguration. Two common threat models are addressed for industrially-driven use cases. The implementation can perform both secure update and reconfiguration without significantly affecting performances.
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Conference papers
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00818735
Contributor : Lionel Torres <>
Submitted on : Monday, April 29, 2013 - 8:56:10 AM
Last modification on : Wednesday, December 18, 2019 - 5:05:04 PM

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CNRS | INSTITUT-TELECOM | SYSMIC | UNIV-BREST | ENIB | LAB-STICC | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER

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Florian Devic, Lionel Torres, Jérémie Crenne, Benoit Badrignans, Pascal Benoit. SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration. FPL: Field Programmable Logic, Aug 2012, Oslo, Norway. pp.57-62, ⟨10.1109/FPL.2012.6339241⟩. ⟨lirmm-00818735⟩

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