SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration

Abstract : Dynamic partial reconfiguration is a growing need for SRAM FPGA-based embedded systems. This feature allows reconfiguring parts of the FPGA while others continue to run. But it may introduce security breaches affecting FPGA configuration. In this paper, a secure protocol to ensure confidentiality, integrity, authenticity and up-to-dateness is described and applied to dynamic partial reconfiguration. Two common threat models are addressed for industrially-driven use cases. The implementation can perform both secure update and reconfiguration without significantly affecting performances.
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Communication dans un congrès
FPL: Field Programmable Logic, Aug 2012, Oslo, Norway. IEEE, 22nd International Conference on Field Programmable Logic and Applications, pp.57-62, 2012, 〈http://www.fpl2012.org〉. 〈10.1109/FPL.2012.6339241〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00818735
Contributeur : Lionel Torres <>
Soumis le : lundi 29 avril 2013 - 08:56:10
Dernière modification le : mardi 16 janvier 2018 - 15:54:20

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Florian Devic, Lionel Torres, Jérémie Crenne, Benoit Badrignans, Pascal Benoit. SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfiguration. FPL: Field Programmable Logic, Aug 2012, Oslo, Norway. IEEE, 22nd International Conference on Field Programmable Logic and Applications, pp.57-62, 2012, 〈http://www.fpl2012.org〉. 〈10.1109/FPL.2012.6339241〉. 〈lirmm-00818735〉

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