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Pre-characterization Procedure for a Mixed Mode Simulation of IR-Drop Induced Delays

Abstract : This paper presents a procedure of pre-characterization dedicated to the logic and timing simulation of IR­drop induced delays in a logic Block Under Test (BUT) embedded in a chip. The proposed pre-characterization is twofold: the pre-characterization of the library on the one hand and the pre-characterization of the power grid on the other hand. Both should be computed only once for a given technology. Based on this pre-characterization, an original algorithm can be built allowing to perform a per-cycle delay simulation of the logic BUT while taking into account the whole chip IR­drop impact on the simulated block. The simulation is based on a realistic resistive model of the Power Distribution Network (PDN).
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00820067
Contributor : Florence Azais <>
Submitted on : Friday, May 3, 2013 - 9:24:33 AM
Last modification on : Monday, August 26, 2019 - 1:38:03 PM

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Marina Aparicio Rodriguez, Mariane Comte, Florence Azaïs, Michel Renovell, Jie Jiang, et al.. Pre-characterization Procedure for a Mixed Mode Simulation of IR-Drop Induced Delays. LATW: Latin American Test Workshop, Apr 2013, Cordoba, Argentina. ⟨10.1109/LATW.2013.6562657⟩. ⟨lirmm-00820067⟩

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