Secure JTAG Implementation Using Schnorr Protocol

Amitabh Das 1, 2 Jean Da Rolt 3 Santosh Ghosh 1, 2 Stefaan Seys 1, 2 Sophie Dupuis 3 Giorgio Di Natale 3 Marie-Lise Flottes 3 Bruno Rouzeyre 3 Ingrid Verbauwhede 1, 2
1 KU-IBBT - FUTURE HEALTH DEPARTMENT [KU Leuven]
KU Leuven - Katholieke Universiteit Leuven
2 ESAT-COSIC - Computer Security and Industrial Cryptography [KU Leuven]
KU-ESAT - Department of Electrical Engineering [KU Leuven]
3 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : The standard IEEE 1149.1 (Test Access Port and Boundary-Scan Architecture, also known as JTAG port) provides a useful interface for embedded systems development, debug, and test. In an 1149.1-compatible integrated circuit, the JTAG port allows the circuit to be easily accessed from the external world, and even to control and observe the internal scan chains of the circuit. However, the JTAG port can be also exploited by attackers to mount several cryptographic attacks. In this paper we propose a novel architecture that implements a secure JTAG interface. Our JTAG scheme allows for mutual authentication between the device and the tester. In contrast to previous work, our scheme uses provably secure asymmetric-key based authentication and verification protocols. The complete scheme is implemented in hardware and integrated with the standard JTAG interface. Detailed area and timing results are also presented.
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Article dans une revue
Journal of Electronic Testing, Springer Verlag, 2013, 29 (2), pp.193-209. 〈10.1007/s10836-013-5369-9〉
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Contributeur : Marie-Lise Flottes <>
Soumis le : lundi 24 juin 2013 - 14:39:41
Dernière modification le : jeudi 28 juin 2018 - 18:44:01
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Amitabh Das, Jean Da Rolt, Santosh Ghosh, Stefaan Seys, Sophie Dupuis, et al.. Secure JTAG Implementation Using Schnorr Protocol. Journal of Electronic Testing, Springer Verlag, 2013, 29 (2), pp.193-209. 〈10.1007/s10836-013-5369-9〉. 〈lirmm-00837904〉

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