Computing Detection Probability of Delay Defects in Signal Line TSVs

Abstract : Three-dimensional stacking technology promises to solve the interconnect bottleneck problem by using Through-Silicon-Vias (TSVs) to vertically connect tiers. However, manufacturing steps may lead to partly broken or incompletely filled TSVs that may degrade the performance and reduce the useful lifetime of a 3D IC. These are latent defects that affect circuit performance and reliability in stacked ICs and can be modeled as small-delay defects (SDDs). Due to combinations of switching activity, supply noise and crosstalk, TSV delays can experience speed-up or slowdown that could let SDDs go undetected by conventional test methods. In this work, we present a metric based on probabilistic delay analysis to detect SDDs induced by resistive opens that occur on signal line TSVs. Our experimental result will show the accurancy of the proposed metric.
Type de document :
Communication dans un congrès
ETS: European Test Symposium, May 2013, Avignon, France. Test Symposium (ETS), 2013 18th IEEE, 2013, 〈10.1109/ETS.2013.6569349〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00839044
Contributeur : Arnaud Virazel <>
Soumis le : jeudi 27 juin 2013 - 09:34:25
Dernière modification le : mardi 25 septembre 2018 - 14:30:02

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Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Computing Detection Probability of Delay Defects in Signal Line TSVs. ETS: European Test Symposium, May 2013, Avignon, France. Test Symposium (ETS), 2013 18th IEEE, 2013, 〈10.1109/ETS.2013.6569349〉. 〈lirmm-00839044〉

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