Skip to Main content Skip to Navigation
Journal articles

A regular fabric design methodology for applications requiring specific layout-level design rules

Sophie Dupuis 1 Noury Ludovic Fel Nicolas 
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Regular fabrics have been introduced as an approach to bridge the gap between ASICs and FPGAs in terms of cost and performance. Indeed, compared to an ASIC, by predefining most of the manufacturing masks, they highly reduce time-to-market, non-recoverable engineering costs and lithography hazards. Also, thanks to hardwired configuration and interconnections their performance is closer to those of ASICs than those of FPGAs. They are therefore well suited to many applications requiring low to medium volume applications or higher performance than those provided by FPGAs. In this paper, we evaluate the interest of using a regular fabric to reduce time and design cost significantly in applications involving specific transistor level design (radiative/spacial conditions, side- channel attacks, NMR environment, etc.). With this aim in view, after a broad state of the art overview with an emphasis on architectures and design flows, we develop our approach of a regular fabric designed to limit layout level design, ad-hoc tools and technological migration cost. Then, we evaluate its performance in a 65 nm process versus FPGA and standard cell based ASIC implementations. For sequential designs, our proposed solution is on average 2.5 slower and 2.3 bigger than a standard cell implantation, but also on average 13 faster than a FPGA.
Complete list of metadata
Contributor : Sophie Dupuis Connect in order to contact the contributor
Submitted on : Monday, April 14, 2014 - 11:55:23 AM
Last modification on : Friday, August 5, 2022 - 10:48:10 AM




Sophie Dupuis, Noury Ludovic, Fel Nicolas. A regular fabric design methodology for applications requiring specific layout-level design rules. Microelectronics Journal, Elsevier, 2013, 45 (2), pp.217-225. ⟨10.1016/j.mejo.2013.11.002⟩. ⟨lirmm-00978481⟩



Record views