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TSVs Pre-Bond Testing: a test scheme for capturing BIST responses

Giorgio Di Natale 1 Marie-Lise Flottes 1 Bruno Rouzeyre 1 Hakim Zimouche 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : The proposed test method aims to detect TSV defects without requiring any contact from a probe-card and thus allows pre-bond testing before wafer thinning. As in previous proposals from the literature, the TSV under test is used by the proposed DfT scheme as a capacitive load and the measure of its charge/discharge delay is used as an indirect measure of its RC parameters. The proposed solution allows testing TSVs individually and at the same time with a small impact of the area overhead for the associated DfT.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00989707
Contributor : Marie-Lise Flottes <>
Submitted on : Monday, May 12, 2014 - 11:58:26 AM
Last modification on : Tuesday, September 1, 2020 - 11:32:04 AM

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  • HAL Id : lirmm-00989707, version 1

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Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche. TSVs Pre-Bond Testing: a test scheme for capturing BIST responses. 3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, CA, United States. ⟨lirmm-00989707⟩

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