3D Design For Test Architectures Based on IEEE P1687
Abstract
3D stacked integrated circuits based on Through Silicon Vias (TSV) are promising with their high performances and small form factor. However, these circuits present many test issues. In this paper we propose a novel 3D Design for Test (DFT) architecture based on IEEE P1687. The proposed test architecture enables test at all 3D fabrication levels: pre, mid, and post-bond levels. We discuss 3 DFT architecture proposals and we show one practical implementation using a commercial EDA tool.
Fichier principal
3DDesignforTestArchitecturesbasedonIEEEP1687.pdf (129.45 Ko)
Télécharger le fichier
| Origin | Files produced by the author(s) |
|---|