3D Design For Test Architectures Based on IEEE P1687

Abstract : 3D stacked integrated circuits based on Through Silicon Vias (TSV) are promising with their high performances and small form factor. However, these circuits present many test issues. In this paper we propose a novel 3D Design for Test (DFT) architecture based on IEEE P1687. The proposed test architecture enables test at all 3D fabrication levels: pre, mid, and post-bond levels. We discuss 3 DFT architecture proposals and we show one practical implementation using a commercial EDA tool.
Type de document :
Communication dans un congrès
3D-TEST'13: Fourth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, California, United States. 2013
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00989717
Contributeur : Marie-Lise Flottes <>
Soumis le : lundi 12 mai 2014 - 12:10:54
Dernière modification le : jeudi 28 juin 2018 - 18:44:01

Identifiants

  • HAL Id : lirmm-00989717, version 1

Collections

Citation

Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, et al.. 3D Design For Test Architectures Based on IEEE P1687. 3D-TEST'13: Fourth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, California, United States. 2013. 〈lirmm-00989717〉

Partager

Métriques

Consultations de la notice

194