3D Design For Test Architectures Based on IEEE P1687

Abstract : 3D stacked integrated circuits based on Through Silicon Vias (TSV) are promising with their high performances and small form factor. However, these circuits present many test issues. In this paper we propose a novel 3D Design for Test (DFT) architecture based on IEEE P1687. The proposed test architecture enables test at all 3D fabrication levels: pre, mid, and post-bond levels. We discuss 3 DFT architecture proposals and we show one practical implementation using a commercial EDA tool.
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Communication dans un congrès
3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, CA, United States. 4th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, 2013
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00989717
Contributeur : Marie-Lise Flottes <>
Soumis le : lundi 12 mai 2014 - 12:10:54
Dernière modification le : mercredi 14 novembre 2018 - 12:49:44

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  • HAL Id : lirmm-00989717, version 1

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Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, et al.. 3D Design For Test Architectures Based on IEEE P1687. 3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, CA, United States. 4th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, 2013. 〈lirmm-00989717〉

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