Power efficiency of embedded systems is a tremendous challenge within the context of platforms with limited power-budget and high computational performance. These conflicting design objectives can be met if both the clock frequency and the supply voltage are dynamically controlled with respect to the ongoing application requirement. As a result, a new trend has appeared in the design of MultiProcessor Systems-on-Chips. It aims at managing the clock frequency and supply voltage of each power domain independently. However, this trend raises some new design challenges. Among them, monitoring at fine-grain and on the fly the operating conditions of each power domain using low-cost on-chip sensors is of great interest. This paper deals with this challenge. It proposes a novel approach based on the integration, either in hardware or in software, of a goodness-of-fit statistical test to interpret data acquired from low-cost and fully digital sensors embedded in each power domain. After a discussion about the accuracy, efficiency and costs of the proposed approach, the voltage reductions that can be achieved for various performance targets are given.