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Journal Articles Future Generation Computer Systems Year : 2005

The instruction register file micro-architecture

Abstract

In this paper, we address the issue of feeding future superscalar processor cores with enough instructions. Hardware techniques targeting an increase in the instruction fetch bandwidth have been proposed such as the trace cache microarchitecture. We present a microarchitecture solution based on a register file holding basic blocks of instructions. This solution places the instruction memory hierarchy out of the cycle determining path. We call our approach, instruction register file (IRF). We estimate our approach with a SimpleScalar based simulator run on the Mediabench benchmark suite and compare to the trace cache performance on the same benchmarks. We show that on this benchmark suite, an IRF-based processor fetching up to three basic blocks per cycle outperforms a trace-cache-based processor fetching 16 instructions long traces by 25% on the average.

Dates and versions

lirmm-01206362 , version 1 (28-09-2015)

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Cite

Bernard Goossens, David Defour. The instruction register file micro-architecture. Future Generation Computer Systems, 2005, Parallel computing technologies, 21 (5), pp.767-773. ⟨10.1016/j.future.2004.05.017⟩. ⟨lirmm-01206362⟩
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