On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell

Abstract : Technology scaling has brought forth major issues related to process variation such as circuit stability and reliability degradation, which are especially problematic for the Static Random Access Memories (SRAM). An accurate and fast estimation of memory reliability is required to ensure its correct operation under extreme conditions. For this reason, several metrics have been proposed, such as the Static Noise Margin (SNM), to evaluate the stability of the SRAM cell under static noise; and the Soft Error Rate (SER), to evaluate the reliability of the memory under radiation. While accurate in predicting the memory reliability, the cell's SER estimation requires lengthy simulations for each cell configuration. On the other hand, a single simulation is necessary to estimate its SNM. For this reason, in this paper we analyze the possibility of using the classical SNM as a first estimator of SRAM cell's reliability under neutron radiation while its transistors are affected by random threshold voltage (Vth) variation. A study based on stability sensitivity analysis to Vth variations leads to a new way of evaluating the SNM metric used to achieve high correlation between SNM and SER.
Type de document :
Communication dans un congrès
DFT: Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2013, New York, United States. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on, pp.143-148, 2013, 〈http://www.dfts.org/dft13/〉. 〈10.1109/DFT.2013.6653597〉
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-01238413
Contributeur : Luigi Dilillo <>
Soumis le : vendredi 4 décembre 2015 - 18:41:27
Dernière modification le : mardi 25 septembre 2018 - 14:30:02

Identifiants

Citation

Ioana Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, et al.. On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFT: Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2013, New York, United States. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on, pp.143-148, 2013, 〈http://www.dfts.org/dft13/〉. 〈10.1109/DFT.2013.6653597〉. 〈lirmm-01238413〉

Partager

Métriques

Consultations de la notice

197