On the Test and Mitigation of Malfunctions in Low-Power SRAMs

Abstract : In low-power SRAMs, power gating mechanisms are commonly used to reduce static power consumption. When the SRAM is not accessed for a long period, such mechanisms allow shutting off one or more memory blocks (core-cell array, address decoder, I/O logic, etc.), thus reducing leakage currents. In order to guarantee static power reduction in low-power SRAMs, reliable operation of power gating mechanisms must be ensured by adequate test techniques. In this paper, we first present a detailed analysis based on electrical simulations to identify faulty behaviors caused by realistic defects that may affect power gating mechanisms embedded in low-power SRAMs. Based on this analysis, we present an efficient test solution targeting detection of observed faulty behaviors. As a final contribution, we propose novel techniques to mitigate the impact of studied defects, once detected by test methods, therefore providing significant yield improvement.
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Article dans une revue
Journal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.611-627. 〈http://link.springer.com/article/10.1007%2Fs10836-014-5479-z〉. 〈10.1007/s10836-014-5479-z〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01238443
Contributeur : Luigi Dilillo <>
Soumis le : vendredi 4 décembre 2015 - 21:43:17
Dernière modification le : jeudi 28 juin 2018 - 18:44:01

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Leonardo Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, et al.. On the Test and Mitigation of Malfunctions in Low-Power SRAMs. Journal of Electronic Testing, Springer Verlag, 2014, 30 (5), pp.611-627. 〈http://link.springer.com/article/10.1007%2Fs10836-014-5479-z〉. 〈10.1007/s10836-014-5479-z〉. 〈lirmm-01238443〉

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