Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures

Abstract : Conventionally, the access failures in SRAMs are treated at core cell level by means of differential bit line voltage analysis. In this work it is shown that under the assumption of random process variability, the conventional approach no longer suffices. It still holds that the differential bit line voltage is degraded by the variability in core cell transistors, but the way this voltage difference is interpreted by the sense amplifier to complete the read operation is influenced by random variability affecting its transistors. Case studies show how variability affecting the sense amplifier can degrade or improve its ability to read the data stored by the core cell, which is itself affected by variability. Using principal component analysis and the SB-SI method, we performed a parametric analysis of the sense amplifier/core cell system and we evaluated the joint probability of access failure. A three times increase in the failure probability has been observed when compared to cell's failure probability. Also, the minimum variability value for which a failure is observed is ~2.5X smaller when joint variability is assumed compared to the case when only the core cell is affected by variability.
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Communication dans un congrès
DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Mar 2013, Abu Dhabi, United Arab Emirates. 8th International Conference on Design Technology of Integrated Systems in Nanoscale Era, pp.39-44, 2013, 〈10.1109/DTIS.2013.6527775〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01248603
Contributeur : Aida Todri-Sanial <>
Soumis le : dimanche 27 décembre 2015 - 21:41:41
Dernière modification le : vendredi 2 mars 2018 - 19:36:02

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Ioana Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, et al.. Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Mar 2013, Abu Dhabi, United Arab Emirates. 8th International Conference on Design Technology of Integrated Systems in Nanoscale Era, pp.39-44, 2013, 〈10.1109/DTIS.2013.6527775〉. 〈lirmm-01248603〉

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