This special issue on advances in design of ultra-low power circuits and systems il- lustrates a broad spectrum of challenges facing designers of high-performance and energy-efficient circuits in emerging technologies. Seeking to improve both the energy efficiency and throughput density, designers have turned to optimization methods tar- geting devices with interconnects to system-level power savings. The articles in this issue represent the cross-layer approach and span various emerging technologies, novel devices, and architectures. This issue contains eight scholarly articles, the experimental results of which show potential/promise to be ultra energy-efficient through innovation in device, logic, and architecture without compromising performance. Each manuscript was assigned to at least three reviewers and has undergone two or more rounds of revisions in the peer- review process. Overall 26 manuscripts were submitted and the following eight articles were selected based on the reviews and scope/fit into the special issue. Gaillardon et al., present a transversal survey on energy-efficient techniques ranging from devices to architectures. They look into various novel device architectures such as fully depleted planar devices, trigate geometries and gate-all-around structures that can allow reaching a high level of performance while reducing power consumption. Exploiting such devices can also lead to innovative circuits and architectural-level power management solutions like adaptive voltage and frequency scaling. Sitik et al., present a 20nm FinFET-based low-swing clocking methodology to pre- serve the dynamic power savings of low-swing clocking while minimizing the effect of leakage power consumption, clock skew, and timing violations. The technique reveals the premise for low-power/high-performance applications while achieving substantial power savings at high switching frequencies. Zhang et al., explore resource pooling where multiple architectural components are shared among the cores for improving system energy efficiency and reducing total chip area for 3D multicore processors. They present a 3D multicore architecture with poolable cache resources and introduce a runtime management policy to improve en- ergy efficiency of 3D systems. Khasanvis et al., introduce a low-power multi-state memory concept based on graphene crossbar devices. They present a multi-state memory design that can store multiple bits in a single cell. This work exploits a bilayer graphene nano-ribbon cross- bar tunneling device that exhibits negative differential resistance and hence can be used as multi-valued logic, which can be implemented along with CMOS lithography. Kang et al., present an overview of the spin-based devices and circuits by adding the spin freedom of electrons for usages such as memories and logic for achieving ultra-low power systems. This tutorial addresses various spin-based memory and logic systems; toggle MRAM, various from of STT-MRAM, Domain-wall systems, Spin-wave logic, partial/dynamic reconfigurable logic systems, and a neuromorphic framework to name a few. Azghadi et al., present a novel neuromorphic system based on a programmable neu- romorphic VLSI device that is comprise of silicon neurons and event-driven synapses, with programmable synaptic weight circuits. The device and neuromorphic system present a real-time low-power computing platform for exploring embedded neuromor- phic event-driven computational systems. Graziano et al., investigate molecular quantum-dot cellular automata (mQCA) as an emerging paradigm for high-performance low-power nanoscale computations. They provide a thorough analysis of mQCA-based circuits and a first assessment on the energy of a mQCA which is the most promising feature of this technology. At the system level, Le et al., investigate energy harvesting techniques for designing autonomous wireless sensor networks. The authors have presented an efficient energy harvesting system, which is compatible with various environmental sources such as light, heat, or wind.