Exploring the impact of functional test programs re-used for power-aware testing
Abstract
High power consumption during at-speed delay fault testing may lead to yield loss and premature aging. On the other hand, reducing too much test power might lead to test escape and reliability problems. Thus, to avoid these issues, test power has to map the power consumed during functional mode. Existing works target the generation of functional test programs able to maximize the power consumption in functional mode of microprocessor cores. The obtained power consumption will be used as threshold to tune the power consumed during testing. This paper investigates the impact of re-using such functional test programs for testing purposes. We propose to apply them by exploiting existing DfT architecture to maximize the delay fault coverage. Then, we combine them with the classical at-speed LOC and LOS delay fault testing schemes to further increase the fault coverage. Results show that it is possible to achieve a global test solution able to maximize the delay fault coverage while respecting the functional power budget.
Keywords
Microprocessor cores
High power consumption
Functional test programs
Functional power budget
At-speed delay fault testing
Power engineering computing
Power aware computing
Microprocessor chips
Integrated circuit testing
Microprocessors
Flip-flops
Power demand
Circuit faults
Clocks
Delays
Testing
ATPG
Functional and Structural test
Power Aware Test
Microprocessor test
Power-aware testing
Premature aging
Yield loss
| Origin | Files produced by the author(s) |
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