A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

Abstract : This paper presents a new hybrid fault-tolerant architecture for robustness improvement of digital CMOS circuits and systems. It targets all kinds of errors in combinational part of logic circuits and thus, can be combined with advanced SEU protection techniques for sequential elements while reducing the power consumption. The proposed architecture combines different types of redundancies: information redundancy for error detection, temporal redundancy for soft error correction and hardware redundancy for hard error correction. Moreover, it uses a pseudo-dynamic comparator for SET and timing errors detection. Besides, the proposed method also aims to reduce power consumption of fault-tolerant architectures while keeping a comparable area overhead compared to existing solutions. Results on the largest ISCAS'85 and ITC'99 benchmark circuits show that our approach has an area cost of about 3 % to 6 % with a power consumption saving of about 33 % compared to TMR architectures.
Type de document :
Article dans une revue
Journal of Electronic Testing, Springer Verlag, 2014, 30 (4), pp.401-413. 〈10.1007/s10836-014-5459-3〉
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-01272958
Contributeur : <>
Soumis le : mardi 17 mai 2016 - 15:14:59
Dernière modification le : jeudi 24 mai 2018 - 15:59:25

Lien texte intégral

Identifiants

Collections

Citation

Ahn Duc Tran, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, et al.. A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. Journal of Electronic Testing, Springer Verlag, 2014, 30 (4), pp.401-413. 〈10.1007/s10836-014-5459-3〉. 〈lirmm-01272958〉

Partager

Métriques

Consultations de la notice

148