To meet the ever-growing demand for higher computing throughput, the clock frequency of the processor was continually increased. After decades of success, this trend stopped at frequencies of 2–3 GHz due to heating issues and energy consumption. To keep pace, multi-core processor architectures began to rise. This, in turn, significantly increased the amount of the SRAM-based cache memory required. As a result, cache memory now occupies large proportion of recent processor chips. In addition, it has become a major source of the leakage power consumption. The power gating technique applied on a SRAM cache is not efficient since it is paid by data loss and by the significant time and the energy required to retrieve the lost data. In this paper, we present three memory cells that can overcome this issue. They combine a conventional volatile CMOS part with magnetic tunnel junctions (MTJs) able to store a data bit in a non-volatile way. Being inherently non-volatile, these hybrid cells enable instantaneous power off and thus complete reduction of the leakage power. Moreover, given that the data bit can be stored in local MTJs and not in distant storage memories, these cells also offer instantaneous and efficient data retrieval. To demonstrate their functionality, the cells are designed using 28 nm FD-SOI technology for the CMOS part and 45 nm round spin transfer torque MTJs (STT-MTJs) with perpendicular magnetization anisotropy. We report the measured performances of the cells in terms of required silicon area, robustness, read/write speed and energy consumption. We also demonstrate that the body-biasing technique offered by the FD-SOI technology can be used to boost the performances of the hybrid cells.