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Conference Papers Year : 2013

Instruction-Driven Timing CPU Model for Efficient Embedded Software Development Using OVP

Abstract

Software development is an important issue in today's MPSoC design. The increasing software complexity makes the functional verification more difficult, resulting into increased development cost [1] [2]. In this context, software engineers are investigating alternatives to scale up the system performance, while dealing with new challenges in MPSoC software development, such as defining inter-CPU communication protocol stacks, as well as porting APIs and operating systems (OSs) [3]. To handle with such scenario virtual platforms are being employed. Virtual platforms emulate hardware behavior at the instruction-level making target software believe that it is running on a real physical hardware. While accelerating the software development, such simulators usually offer a set of CPU models and memory system models, allowing the analyses of executing different application/OSs onto multiprocessor architectures without modifications.
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lirmm-01419122 , version 1 (18-12-2016)

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Felipe da Rosa, Luciano Ost, Ricardo Reis, Gilles Sassatelli. Instruction-Driven Timing CPU Model for Efficient Embedded Software Development Using OVP. ICECS: International Conference on Electronics, Circuits, and Systems, Dec 2013, Abu Dhabi, United Arab Emirates. pp.855-858, ⟨10.1109/ICECS.2013.6815549⟩. ⟨lirmm-01419122⟩
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