Embedded memory hierarchy exploration based on magnetic RAM

Abstract : SRAM, DRAM and FLASH are the three main employed technologies in design of on-chip processor memories. However, manufacturing constraints for this technologies in the most advanced nodes compromises further evolution. MRAM (Magnetic memory) presents itself as an attractive alternative for these technologies, as it has reasonable timing and power characteristics. Last results in the state of the art demonstrate that MRAM access time is can be less than 5ns and read/write energy per bit in same order of magnitude as SRAM, also it can evolve with the manufacturing process. One important feature of MRAM is the non-volatility, allowing to define new instant on/off policies and mainly optimizing leakage current. In this paper we demonstrate how MRAM can be used into memory hierarchy of embedded systems. The main objective is to demonstrate the interest to use MRAM for Level-1 & 2 cache and to better understand the architectural choice in order to minimize the impact of the higher write latency of MRAMs.
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Communication dans un congrès
FTFC: Faible Tension Faible Consommation, Jun 2013, Paris, France. IEEE Faible Tension Faible Consommation, 2013, 〈10.1109/FTFC.2013.6577780〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01419132
Contributeur : Gilles Sassatelli <>
Soumis le : dimanche 18 décembre 2016 - 20:46:31
Dernière modification le : jeudi 28 juin 2018 - 15:11:59
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Luís Vitório Cargnini, Lionel Torres, Raphael Martins Brum, Sophiane Senni, Gilles Sassatelli. Embedded memory hierarchy exploration based on magnetic RAM. FTFC: Faible Tension Faible Consommation, Jun 2013, Paris, France. IEEE Faible Tension Faible Consommation, 2013, 〈10.1109/FTFC.2013.6577780〉. 〈lirmm-01419132〉

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