Scan-Chain Intra-Cell Aware Testing

Abstract : This paper first presents an evaluation of the effectiveness of different test pattern sets in terms of ability to detect possible intra-cell defects affecting the scan flip-flops. The analysis is then used to develop an effective test solution to improve the overall test quality. As a major result, the paper demonstrates that by combining test vectors generated by a commercial ATPG to detect stuck-at and delay faults, plus a fragment of extra test patterns generated to specifically target the escaped defects, we can obtain a higher intra-cell defect coverage (i.e., 6.46% on average) and a shorter test time (i.e., 42.20% on average) than by straightforwardly using an ATPG which directly targets these defects.
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Article dans une revue
IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2016, PP (99), In press. 〈10.1109/TETC.2016.2624311〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01430859
Contributeur : Alberto Bosio <>
Soumis le : mardi 10 janvier 2017 - 13:01:11
Dernière modification le : jeudi 28 juin 2018 - 18:44:01

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Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Matteo Sonza Reorda, et al.. Scan-Chain Intra-Cell Aware Testing. IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2016, PP (99), In press. 〈10.1109/TETC.2016.2624311〉. 〈lirmm-01430859〉

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